PROPHET 3000 disassembled boot eprom

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Prophet 3000 Memory Map


note: A19 - A23 of 68HC000 not connected

    address (hex)
low		high		decimal bytes		device
----------------------------------------------------------------------------
0x000000	0x003fff	16K			boot eprom

0x02[01]xxx	IOCS region
0x020000	0x0200ff				floppy
0x020200	0x020202	4 (even)		midi uart
0x020400	0x020401	2?			a/d converter
0x020600	0x0206ff	256(even)		I-627
0x020800	0x02087f	128			S&H DAC
0x020a00	0x020a00	1			clears dma intr
0x020c00	0x020c00	1		misc out- floppy, a/d filter
0x020e01	0x020e01	1		misc in- ready signals
0x021000	0x021000	1?		clim sec? (B) I-630
0x021200	0x02120f	16?			scsi
0x021400	0x021400	1?			sram
0x021600	0x021600	1?			floppy operation
0x021800	0x021800	1?			floppy con
0x021a00	0x021a00	1?			read smpte
0x021c00	0x021c00	1?			write smpte
0x021e00	0x021e02	4 (even)		ctrl panel uart

0x040000	0x07ffff	256k			scratchpad ram

hardware interrupt vectors:
level 1: 040024
level 2: 04002a
level 3: 040030
level 4: 040036
level 5: 040038
level 6: 04003e
level 7: 04001e (not used -- same vector as most exceptions)


device notes:

boot eprom (2 x 27C64):
  chip enable: ROMCS
  eproms (16k).


floppy controller (WD 37C65):
  chip enable: FLOPPY
  need info/data sheets on this


midi uart (68B50):
  chip enable: MUART
  vanilla midi uart, addressed with 2 consecutive even addresses


a/d converter (2 x 74HC595)
  chip enable: ADC
audio sample data is input serially via these two shift registers.
Reading from this address latches the 16 bit value onto the 68k's data
bus.  I'm guessing the a/d must be polled to check when a sample is
ready to be read into main memory.  Check data sheet for CX20018.


I-627
  chip enable: I-627
semi-custom chip.  Handles interface between 68k and sample memory
(yup- the 68k doesn't directly touch the sample ram).  Has a good
chunk of 68k address space devoted to it...any info on this chip would
be very useful.


S&H DAC
  chip enable: SHDAC
writing to this address space handles all audio output.  D4-15 get
latched to a 12 bit D/A converter which get routed to a CEM3387 for a
particular voice (based on the address).  This controls the cutoff
freq, volume, pan, resonance and 3 pole cv (?) of any of the CEM3387
chips.  I think two writes are necessary: the first to send the 12
bits to the D/A converter, the second to actually latch the value onto
the 3357 (check the 3357 data sheet to confirm).

The SHDAC line is also responsible for latching the sample data into
I-629. Here the 16 bit value is serially converted and sent to 1 of 8
PCM56P D/A converters.  (how does the sample get from sample memory to
I-629?)


clear dma intr
  chip enable: CLRDMA
enabling this address clears the flip flop that signals a dma
interrupt.


miscalenous outputs
  chip enable: MISCOUT
D8-13 of the data bus get latched into an HC174.  These control
various outputs:

D8: this sets/clears a relay which controls the left/right main
outputs.  The main audio outputs can be enabled/disabled by this bit.

D9,10: filter select.  Selects which lowpass filter the sample input
uses, both for left and right channel.  Decoding:
D9 D10  filter
-- ---  ------
0   0   20 khz
0   1   12 khz
1   0    6 khz
1   1   n/c (ground)

D11:  motor on.  Turns on the motor for the 3.5" floppy drive

D12: TC. ??? some input on the floppy controller

D13: FLOPRST.  Resets the WD 37C65 floppy controller.


miscallenous inputs
  chip enable: MISCIN
like miscout, but this is a read only address.  Data bits D0 - D5 can
be read for the following info:

D0: ADCRDY.  Signals that the A/D converter is ready.  This signal is
generated by I-630, one of the custom chips.

D1: CC.  No clue what it's for, generated by I-630 and also goes to
the CX20018 A/D converter.

D2: SMPTERDY.  signals that the SMPTE cpu is ready for a write.

D3: this is the state of the footswitch input.

D4: INDEX.  Generated by the WD 37C65 floppy controller (IDX).

D5: DISKINT.  The floppy controller is requesting an interrupt
(hmm... this must be polled).


clim sec
  chip enable: CLIMSEC
enabling this address sets the CLIMSEC line on I-630.  No clue what it
does.


scsi
  chip enable: SCSI
enables the I-628 and probably the NCR5380 chips.  Note that D0-7 on
both I-628 and NCR5380 can toy with the 68k's data bus through the
DBSEL line from I-628.


sram
  chip enable: SRAM
through I-628, this enables the sample ram.  No clue on how.


floppy operation
  chip enable: FLDOP
enables the floppy controller line LDOP.

floppy con
  chip enable: FLDCON
enables the floppy controller line LDCR.


read smpte
  chip enable: RDSMPTE
clears the interrupt generrated by incoming smpte.  Latches 8 bits of
data from smpte cpu onto 68k data bus.


write smpte
  chip enable: WRSMPTE
sets interrupt on smpte cpu.  8 bits of data from 68k data bus is
latched into register for smpte cpu to read.

ctrl panel uart
  chip enable: CPUART
enables 68B50 uart for reading/writing to control panel.


scratchpad ram
  chip enable: RAS/CAS/OE generated by I-630
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